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EP2C35A15F324C6N Datasheet(PDF) 25 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 25 Page - Altera Corporation |
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25 / 168 page  Altera Corporation 2–13 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Figure 2–9. Register Chain Interconnects The C4 interconnects span four LABs, M4K blocks, or embedded multipliers up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–10 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including PLLs, M4K memory blocks, embedded multiplier blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor (see Figure 2–10) can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. LE 1 LE 2 LE 3 LE 4 LE 5 LE 6 LE 7 LE 8 LE 9 LE 10 LE 11 LE 12 LE13 LE 14 LE 15 LE 16 Carry Chain Routing to Adjacent LE Local Interconnect Register Chain Routing to Adjacent LE's Register Input Local Interconnect Routing Among LEs in the LAB |
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