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EP2C35A15F324C6N Datasheet(PDF) 20 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 20 Page - Altera Corporation |
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20 / 168 page  2–8 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Logic Array Blocks LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, M4K RAM blocks, and embedded multipliers from the left and right can also drive an LAB’s local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 48 LEs through fast local and direct link interconnects. Figure 2–6 shows the direct link connection. Figure 2–6. Direct Link Connection LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include: ■ Two clocks ■ Two clock enables ■ Two asynchronous clears ■ One synchronous clear ■ One synchronous load LAB Direct link interconnect to right Direct link interconnect from right LAB, M4K memory block, embedded multiplier, PLL, or IOE output Direct link interconnect from left LAB, M4K memory block, embedded multiplier, PLL, or IOE output Local Interconnect Direct link interconnect to left |
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