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EP2C35A15F324C6N Datasheet(PDF) 18 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 18 Page - Altera Corporation |
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18 / 168 page  2–6 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Logic Elements Figure 2–4. LE in Arithmetic Mode The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 16 LEs by automatically linking LABs in the same column. For enhanced fitting, a long carry chain runs vertically, which allows fast horizontal connections to M4K memory blocks or embedded multipliers through direct link interconnects. For example, if a design has a long carry chain in a LAB column next to a column of M4K memory blocks, any LE output can feed an adjacent M4K memory block through the direct link interconnect. Whereas if the carry chains ran horizontally, any LAB not next to the column of M4K memory blocks would use other row or column interconnects to drive a M4K memory block. A carry chain continues as far as a full column. clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) CLRN D Q ENA Register chain connection sclear (LAB Wide) sload (LAB Wide) Register chain output Row, column, and direct link routing Row, column, and direct link routing Local routing Register Feedback Three-Input LUT Three-Input LUT cin (from cout of previous LE) data2 data1 cout |
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