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EP2C35A15F324C6N Datasheet(PDF) 14 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 14 Page - Altera Corporation |
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14 / 168 page  2–2 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Logic Elements phase-align double data rate (DDR) signals) provide interface support for external memory devices such as DDR, DDR2, and single data rate (SDR) SDRAM, and QDRII SRAM devices at up to 167 MHz. Figure 2–1 shows a diagram of the Cyclone II EP2C20 device. Figure 2–1. Cyclone II EP2C20 Device Block Diagram The number of M4K memory blocks, embedded multiplier blocks, PLLs, rows, and columns vary per device. Logic Elements The smallest unit of logic in the Cyclone II architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE features: ■ A four-input look-up table (LUT), which is a function generator that can implement any function of four variables ■ A programmable register ■ A carry chain connection ■ A register chain connection ■ The ability to drive all types of interconnects: local, row, column, register chain, and direct link interconnects ■ Support for register packing ■ Support for register feedback PLL PLL IOEs PLL PLL IOEs IOEs Logic Array Logic Array Logic Array Logic Array IOEs M4K Blocks M4K Blocks Embedded Multipliers |
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