EP2C35A15F324C6N datasheet(99/168 Pages) ALTERA

Part #	EP2C35A15F324C6N

Description	Cyclone II Device Family

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Manufacturer	ALTERA [Altera Corporation]

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99 / 168 page

Altera Corporation

5–9

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Table 5–8 shows the recommended operating conditions for user I/O

pins with differential I/O standards.

Table 5–8. Recommended Operating Conditions for User I/O Pins Using Differential Signal I/O Standards

I/O

Standard

VCCIO (V)

VID (V) (1)

VICM (V)

VIL (V)

VIH (V)

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Max

Min

Max

LVDS

2.375

2.5

2.625

0.1

—

0.65

0.1

—

2.0

—

Mini-LVDS

(2)

2.375

2.5

2.625

—

————

—

RSDS (2)

2.375

2.5

2.625

—

————

—

LVPECL

(3) (6)

3.135

3.3

3.465

0.1

0.6

0.95

—

0

2.2

2.1

2.88

Differential

1.5-V HSTL

class I

and II (4)

1.425

1.5

1.575

0.2

—

VCCIO

+ 0.6

0.68

—

0.9

—

VREF

– 0.20

VREF

+ 0.20

—

Differential

1.8-V HSTL

class I

and II (4)

1.71

1.8

1.89

—

————

—

VREF

– 0.20

VREF

+ 0.20

—

Differential

SSTL-2

class I

and II (5)

2.375

2.5

2.625

0.36

—

VCCIO

+ 0.6

0.5 ×

VCCIO

– 0.2

0.5 ×

VCCIO

0.5 ×

VCCIO

+ 0.2

—VREF

– 0.35

VREF

+ 0.35

—

Differential

SSTL-18

class I

and II (5)

1.7

1.8

1.9

0.25

—

VCCIO

+ 0.6

0.5 ×

VCCIO

– 0.2

0.5 ×

VCCIO

0.5 ×

VCCIO

+ 0.2

—VREF

– 0.25

VREF

+ 0.25

—

Notes to Table 5–8:

(1)

Refer to the High-Speed Differential Interfaces in Cyclone II Devices chapter of the Cyclone II Device Handbook for

measurement conditions on VID.

(2)

The RSDS and mini-LVDS I/O standards are only supported on output pins.

(3)

The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output

pins.

(4)

The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock

pins.

(5)

The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock

pins.

(6)

The LVPECL clock inputs are powered by VCCINT and support all VCCIO settings. However, it is recommended to

connect VCCIO to typical value of 3.3V.

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