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EP2C35A15F324C6N Datasheet(PDF) 85 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 85 Page - Altera Corporation |
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85 / 168 page  Altera Corporation 4–3 February 2007 Cyclone II Device Handbook, Volume 1 Hot Socketing & Power-On Reset the power supply can provide current to the device’s VCC and ground planes. This condition can lead to latch-up and cause a low-impedance path from VCC to ground within the device. As a result, the device extends a large amount of current, possibly causing electrical damage. Altera has ensured by design of the I/O buffers and hot-socketing circuitry, that Cyclone II devices are immune to latch-up during hot socketing. Hot-Socketing Feature Implementation in Cyclone II Devices The hot-socketing feature turns off the output buffer during power up (either VCCINT or VCCIO supplies) or power down. The hot-socket circuit generates an internal HOTSCKT signal when either VCCINT or VCCIO is below the threshold voltage. Designs cannot use the HOTSCKT signal for other purposes. The HOTSCKT signal cuts off the output buffer to ensure that no DC current (except for weak pull-up leakage current) leaks through the pin. When VCC ramps up slowly, VCC is still relatively low even after the internal POR signal (not available to the FPGA fabric used by customer designs) is released and the configuration is finished. The CONF_DONE, nCEO, and nSTATUS pins fail to respond, as the output buffer cannot drive out because the hot-socketing circuitry keeps the I/O pins tristated at this low VCC voltage. Therefore, the hot-socketing circuit has been removed on these configuration output or bidirectional pins to ensure that they are able to operate during configuration. These pins are expected to drive out during power-up and power-down sequences. Each I/O pin has the circuitry shown in Figure 4–1. |
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