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EP2C35A15F324C6N Datasheet(PDF) 65 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 65 Page - Altera Corporation |
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65 / 168 page  Altera Corporation 2–53 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture f For more information on Cyclone II supported I/O standards, see the Selectable I/O Standards in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook. High-Speed Differential Interfaces Cyclone II devices can transmit and receive data through LVDS signals at a data rate of up to 640 Mbps and 805 Mbps, respectively. For the LVDS transmitter and receiver, the Cyclone II device’s input and output pins support serialization and deserialization through internal logic. Differential HSTL-15 class I or class II Pseudo differential (4) (5) 1.5 V v (7) 1.5 V (5) v (6) v (6) Differential HSTL-18 class I or class II Pseudo differential (4) (5) 1.8 V v (7) 1.8 V (5) v (6) v (6) LVDS Differential 2.5 V 2.5 V vvv v v RSDS and mini-LVDS (8) Differential (5) 2.5 V vv v LVPECL (9) Differential 3.3 V/ 2.5 V/ 1.8 V/ 1.5 V (5) vv Notes to Table 2–17: (1) To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and turn on the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II software. (2) These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs. (3) PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and bottom I/O pins. (4) Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and SSTL inputs and only decode one of them. (5) This I/O standard is not supported on these I/O pins. (6) This I/O standard is only supported on the dedicated clock pins. (7) PLL_OUT does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II. (8) mini-LVDS and RSDS are only supported on output pins. (9) LVPECL is only supported on clock inputs. Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2) I/O Standard Type VCCIO Level Top & Bottom I/O Pins Side I/O Pins Input Output CLK, DQS User I/O Pins CLK, DQS PLL_OUT User I/O Pins |
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