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EP2C35A15F324C6N Datasheet(PDF) 63 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 63 Page - Altera Corporation |
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63 / 168 page  Altera Corporation 2–51 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Slew Rate Control Slew rate control is performed by using programmable output drive strength. Bus Hold Each Cyclone II device user I/O pin provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated. The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent overdriving signals. 1 If the bus-hold feature is enabled, the device cannot use the programmable pull-up option. Disable the bus-hold feature when the I/O pin is configured for differential signals. Bus hold circuitry is not available on the dedicated clock pins. The bus-hold circuitry is only active after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k Ωto pull the signal level to the last-driven state. Refer to the DC Characteristics & Timing Specifications chapter in Volume 1 of the Cyclone II Device Handbook for the specific sustaining current for each VCCIO voltage level driven through the resistor and overdrive current used to identify the next driven input level. Programmable Pull-Up Resistor Each Cyclone II device I/O pin provides an optional programmable pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor (typically 25 k Ω) holds the output to the VCCIO level of the output pin’s bank. 1 If the programmable pull-up is enabled, the device cannot use the bus-hold feature. The programmable pull-up resistors are not supported on the dedicated configuration, JTAG, and dedicated clock pins. |
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