 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EP2C35A15F324C6N Datasheet(PDF) 59 Page - Altera Corporation |
|
|
|||||||||||||||||||||||||||||
EP2C35A15F324C6N Datasheet(HTML) 59 Page - Altera Corporation |
|
|
59 / 168 page  Altera Corporation 2–47 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture You can use any of the DQ pins for the parity pins in Cyclone II devices. The Cyclone II device family supports parity in the ×8/×9, and ×16/×18 mode. There is one parity bit available per eight bits of data pins. The data mask, DM, pins are required when writing to DDR SDRAM and DDR2 SDRAM devices. A low signal on the DM pin indicates that the write is valid. If the DM signal is high, the memory masks the DQ signals. In Cyclone II devices, the DM pins are assigned and are the preferred pins. Each group of DQS and DQ signals requires a DM pin. When using the Cyclone II I/O banks to interface with the DDR memory, at least one PLL with two clock outputs is needed to generate the system and write clock. The system clock is used to clock the DQS write signals, commands, and addresses. The write clock is shifted by –90° from the system clock and is used to clock the DQ signals during writes. Figure 2–27 illustrates DDR SDRAM interfacing from the I/O through the dedicated circuitry to the logic array. EP2C35 484-pin FineLine BGA 16 (4) 888 672-pin FineLine BGA 20 (4) 888 EP2C50 484-pin FineLine BGA 16 (4) 888 672-pin FineLine BGA 20 (4) 888 EP2C70 672-pin FineLine BGA 20 (4) 888 896-pin FineLine BGA 20 (4) 888 Notes to Table 2–15: (1) Numbers are preliminary. (2) EP2C5 and EP2C8 devices in the 144-pin TQFP package do not have any DQ pin groups in I/O bank 1. (3) Because of available clock resources, only a total of 6 DQ/DQS groups can be implemented. (4) Because of available clock resources, only a total of 14 DQ/DQS groups can be implemented. (5) The ×9 DQS/DQ groups are also used as ×8 DQS/DQ groups. The ×18 DQS/DQ groups are also used as ×16 DQS/DQ groups. (6) For QDRI implementation, if you connect the D ports (write data) to the Cyclone II DQ pins, the total available ×9 DQS /DQ and ×18 DQS/DQ groups are half of that shown in Table 2–15. Table 2–15. Cyclone II DQS & DQ Bus Mode Support (Part 2 of 2) Note (1) Device Package Number of ×8 Groups Number of ×9 Groups (5), (6) Number of ×16 Groups Number of ×18 Groups (5), (6) |
Similar Part No. - EP2C35A15F324C6N |
|
Similar Description - EP2C35A15F324C6N |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
