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EP2C35A15F324C6N Datasheet(PDF) 58 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 58 Page - Altera Corporation |
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58 / 168 page  2–46 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 I/O Structure & Features Figure 2–26. Cyclone II Device DQ & DQS Groups in ×8/×9 Mode Notes (1), (2) Notes to Figure 2–26: (1) Each DQ group consists of a DQS pin, DM pin, and up to nine DQ pins. (2) This is an idealized pin layout. For actual pin layout, refer to the pin table. Cyclone II devices support the data strobe or read clock signal (DQS) used in DDR and DDR2 SDRAM. Cyclone II devices can use either bidirectional data strobes or unidirectional read clocks. The dedicated external memory interface in Cyclone II devices also includes programmable delay circuitry that can shift the incoming DQS signals to center align the DQS signals within the data window. The DQS signal is usually associated with a group of data (DQ) pins. The phase-shifted DQS signals drive the global clock network, which is used to clock the DQ signals on internal LE registers. Table 2–15 shows the number of DQ pin groups per device. DQ Pins DQS Pin DM Pin DQ Pins (2) Table 2–15. Cyclone II DQS & DQ Bus Mode Support (Part 1 of 2) Note (1) Device Package Number of ×8 Groups Number of ×9 Groups (5), (6) Number of ×16 Groups Number of ×18 Groups (5), (6) EP2C5 144-pin TQFP (2) 3 300 208-pin PQFP 7 (3) 433 EP2C8 144-pin TQFP (2) 3 300 208-pin PQFP 7 (3) 433 256-pin FineLine BGA® 8 (3) 444 EP2C15 256-pin FineLine BGA 8 4 4 4 484-pin FineLine BGA 16 (4) 888 EP2C20 256-pin FineLine BGA 8 4 4 4 484-pin FineLine BGA 16 (4) 888 |
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