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EP2C35A15F324C6N Datasheet(PDF) 54 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 54 Page - Altera Corporation |
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54 / 168 page  2–42 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 I/O Structure & Features Figure 2–24. Control Signal Selection per IOE In normal bidirectional operation, you can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. You can use the output register for data requiring fast clock-to-output performance. The OE register is available for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from the local interconnect in the associated LAB, dedicated I/O clocks, or the column and row interconnects. All registers share sclr and aclr, but each register can individually disable sclr and aclr. Figure 2–25 shows the IOE in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset Dedicated I/O Clock [5..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect oe io_coe io_caclr Local Interconnect io_csclr io_cce_out io_cce_in io_cclk |
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