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EP2C35A15F324C6N Datasheet(PDF) 46 Page - Altera Corporation |
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EP2C35A15F324C6N Datasheet(HTML) 46 Page - Altera Corporation |
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46 / 168 page  2–34 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Embedded Multipliers Figure 2–18. Multiplier Block Architecture Note to Figure 2–18: (1) If necessary, these signals can be registered once to match the data signal path. Each multiplier operand can be a unique signed or unsigned number. Two signals, signa and signb, control the representation of each operand respectively. A logic 1 value on the signa signal indicates that data A is a signed number while a logic 0 value indicates an unsigned number. Table 2–11 shows the sign of the multiplication result for the various operand sign representations. The result of the multiplication is signed if any one of the operands is a signed value. CLRN DQ ENA Data A Data B aclr clock ena signa (1) signb (1) CLRN DQ ENA CLRN DQ ENA Data Out Embedded Multiplier Block Output Register Input Register Table 2–11. Multiplier Sign Representation Data A (signa Value) Data B (signb Value) Result Unsigned Unsigned Unsigned Unsigned Signed Signed Signed Unsigned Signed Signed Signed Signed |
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