 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
F85226 Datasheet(PDF) 10 Page - Feature Integration Technology Inc. |
|
|
|||||||||||||||||||||||||||||
F85226 Datasheet(HTML) 10 Page - Feature Integration Technology Inc. |
|
|
10 / 44 page  Fintek Feature Integration Technology Inc. F85226 July, 2007 V0.25P 5 F85226 14 PCIRST# INts VDD3v PCI system reset used for the LPC bus. The Reset signal line can be connected to PCIRST# signal on the host. 23 SERIRQ I/O24ts VDD3v Serial IRQ Input/Output. 22 LDRQ# O24 VDD3v Encoded DMA Request signal. 24 PWRDN# INts VDD3v Power Down. The signal is active low according to CR 44 Bit 7and wake-up enable by hardware setting. There are eight different power-down states (Power down Mode 3). 6.4 ISA interface Pin No. Pin Name Type PWR Description 58-56 SA[19:17] I/O24ts_u100k (5V-tolerance) VDD3v System Address Bus. These are the upper addresses that define the ISA’s byte address space (up to 1 M byte). The SA [19:17] are at tri-states during PCIRST#. 54-51 49-46 44-41 35-31 SA[16:0] I/O24ts_u100k (5V-tolerance) VDD3v System Address Bus. These define the ISA’s byte address space (up to 128K byte). The SD [16:0] are at tri-states during PCIRST#. 122-121 119-114 75-71 69-67 SD[15:0] I/O24ts_u100k (5V-tolerance) VDD3v System Data Bus. These provide 16-bit data for devices to reside on the ISA Bus. The SD [15:0] are at tri-states during PCIRST#. 59 AEN O24 (5V-tolerance) VDD3v Address Enable. AEN is asserted during DMA cycles, driven high during F85226 initiated refresh cycles, driven low upon PCIRST#. 86 IOR# I/O24ts_u100k (5V-tolerance) VDD3v I/O Read. IOR# is asserted to request an ISA I/O slave to drive data onto the data bus. 84 IOW# I/O24ts_u100k (5V-tolerance) VDD3v I/O Write. IOW# is asserted to request an ISA I/O slave to accept data from the data bus. 61 IOCHRDY I/O24ts (5V-tolerance) VDD3v I/O Channel Ready. IOCHDRY asserted indicates that an ISA slave requires additional wait states. When the F85226 is an ISA slave, IOCHRDY is an output indicating additional wait states are required. 92 SYSCLK O24 VDD3v ISA System Clock. SYSCLK offers the reference clock to the ISA bus. The frequency is generated from dividing PCICLK by 3 or 4 (select by CR06 bit7). 77 RSTDRV O24 VDD3v Reset Drive. RSTDRV asserted indicates to reset devices that reside on the ISA Bus while the PCIRST# has been asserted. |
Similar Part No. - F85226 |
|
Similar Description - F85226 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
