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F75373S Datasheet(PDF) 27 Page - Feature Integration Technology Inc. |
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F75373S Datasheet(HTML) 27 Page - Feature Integration Technology Inc. |
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27 / 49 page  Fintek Feature Integration Technology Inc. V0.25P 22 F75373 automatically adjusted according to FAN2 EXPECT register. 01: FAN2 operates in TEMPERATURE mode. PWMOUT2 duty-cycle is automatically adjusted according to FAN2 EXPECT register, which will be automatically loaded into preset values according to the current temperature. (When PIN3 power-on trapped to 1, this mode is selected after power-on.) 1X: FAN2 operates in MANUAL mode. Software set the PWMOUT2 duty-cycle directly. 5-4 FAN1_MODE R/W 00: FAN1 operates in SPEED mode. PWMOUT1 duty-cycle is automatically adjusted according to FAN1 EXPECT register. 01: FAN1 operates in TEMPERATURE mode. PWMOUT1 duty-cycle is automatically adjusted according to FAN1 EXPECT register, which will be automatically loaded into preset values according to the current temperature. (When PIN3 power-on trapped to 1, this mode is selected after power-on.) 1X: FAN1 operates in MANUAL mode. Software set the PWMOUT1 duty-cycle directly. 3 Reserved 2 KEEP_DROP_DU TY2 R/W Set to 1, keep PWMOUT2 duty-cycle decrease to DROP duty and hold. 1 KEEP_DROP_DU TY1 R/W Set to 1, keep PWMOUT1 duty-cycle decrease to DROP duty and hold. 0 EN_RESET_TIME R R/W Set to 1, enable interface_idle timer. Set to 0, disable the timer. When the timer is enabled, if software doesn’t access the this chip through GP_CLK and GP_DATA, the reset timer starts to count down according to the value set in INDEX 62H. When it counts down to zero, INDEX[72H, 73H] will be loaded into INDEX[74H,75H]. 6.19 Fan Fault Time Register -- Index 61h Power on default: B4h Bit Name Attribute Description 7-0 F_FAULT_TIME R/W This register determines the time of fan fault. Two conditions cause fan fault event: |
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