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F72820 Datasheet(PDF) 9 Page - Feature Integration Technology Inc. |
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F72820 Datasheet(HTML) 9 Page - Feature Integration Technology Inc. |
9 / 18 page ![]() F72820 Jul 2007 V0.24P -6- F72820 VOUT Q1 Q2 UGATE LGATE PHASE BOOT VIN = 5V OCSET 40uA R OCSET OC i D VDS VSET V PHASE =VIN - VDS V OCSET =VIN - VSET OVER-CURRENT TRIP: VDS VSET > I OCSET I D xR DS(ON) >I OCSET xR OCSET Figure 6 6.5 Under-voltage Protection Pins FB are monitored during converter operation by under-voltage (UV) comparators. If the FB voltage drops below 0.5V, a fault signal is generated. The internal fault logic shut down regulator simultaneously when the fault signal triggers a restart. At time t0, VOUT has dropped below 0.5V of the nominal output voltage. Output is quickly shut down and the internal soft-start function begins producing soft-start ramps. The delay interval, t0 to 3*tss, seen by the output is equivalent to three soft-start cycles. After a short delay interval of 10.5ms, the fourth internal soft-start cycle initiates a normal soft-start ramp of the output, at time 3*tss. Both outputs are brought back into regulation by time 4*tss, as long as the UV event has cleared. When the cause of the UV still been present after the delay interval. A fault signal could then be generated and the outputs once again shutdown. t0 tss 2tss 3tss 4tss TIME 0V 1.5V 3V Delay interval VOUT Figure 7 |
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