8

5194F–SEEPR–1/08

AT24C1024B

Figure 4-5.

Start and Stop Definition

Figure 4-6.

Output Acknowledge

5. Device Addressing

The 1024K EEPROM requires an 8-bit device address word following a start condition to enable

the chip for a read or write operation (see Figure 7-1 on page 11). The device address word con-

sists of a mandatory one, zero sequence for the first four most significant bits as shown. This is

common to all two-wire EEPROM devices.

The 1024K uses the two device address bit, A1, A2, to allow up to four devices on the same bus.

These A1, A2 bits must compare to the corresponding hardwired input pins. The A1, A2 pin uses

an internal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.

address bit is the most significant bit of the data word address that follows. The eighth bit of the

device address is the read/write operation select bit. A read operation is initiated if this bit is high

and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not

made, the device will return to a standby state.

SDA

SCL

START

STOP

SCL

DATA IN

DATA OUT

START

ACKNOWLEDGE

9

8

1