AT24C1024BN-SH25-T datasheet(7/25 Pages) ATMEL

7 / 25 page

7

5194F–SEEPR–1/08

AT24C1024B

Figure 4-3.

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Note:

1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4-4.

Data Validity

t

wr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

SCL

DATA STABLE

DATA

CHANGE

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