6

5194F–SEEPR–1/08

AT24C1024B

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which

must precede any other command (see Figure 4-5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a

read sequence, the Stop command will place the EEPROM in a standby power mode (see Fig-

ure 4-5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-

edge that it has received each word.

STANDBY MODE: The AT24C1024B features a low-power standby mode which is enabled: a)

upon power-up and b) after the receipt of the stop bit and the completion of any internal

operations.

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire

part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9

cycles, (c) create another start bit followed by stop bit condition as shown below. The device is

ready for next communication after above steps have been completed.

Figure 4-1.

Software Reset

Figure 4-2.

Start bit

Stop bit

Start bit

Dummy Clock Cycles

SCL

SDA

12

3

8

9

SCL

SDA IN

SDA OUT

t

F

t

HIGH

t

LOW

t

LOW

t

R

t

AA

t

DH

t

BUF

t

SU.STO

t

SU.DAT

t

HD.DAT

t

HD.STA

t

SU.STA