3

4743D–CORD–03/06

U4082B

2.

Pin Configuration

Figure 2-1.

Pinning SO28

1

2

3

4

5

6

7

8

10

9

27

22

21

20

18

19

17

12

11

28

25

26

23

24

HTO-

HTI

TO

TI

MICO

MIC

VS

HTO+

MUTE

CD

FI

FO

TLI1

RECO

RI

RLI2

RLO2

TLO2

RLO1

TLO1

TLI2

RLI1

CPR

GND

16

15

14

13

VCI

CT

CPT

VB

Table 2-1.

Pin Description

Pin

Symbol

Function

1

FO

Filter output. Output impedance is less than 50

Ω

2

FI

Filter input. Input impedance is greater than 1 M

Ω

3CD

Chip disable. A logic low (< 0.8V) sets normal operation. A logic high (> 2V) disables the IC to conserve

power. Input impedance is nominally 90 k

Ω

4VS

Supply voltage 2.8V to 6.5V, approximately 5 mA. AGC circuit reduces the receive attenuator gain at

25 dB, receive mode at 2.8V

5HTO+

Output of the second hybrid amplifier (Hybrid output). Gain is internally set at –1 to provide a differential

output, (in conjunction with HTO–) to the hybrid transformer

6

HTO–

Output of the first hybrid amplifier. Hybrid output. Gain is set by external resistors

7

HTI

Input and summing node for the first hybrid amplifier. DC level is approximately V

B

8

TO

Transmit attenuator output. DC level is approximately V

B

9

TI

Transmit attenuator input. Maximum signal level is 350 mVrms. Input impedance is approximately 10 k

Ω

10

MICO

Microphone amplifier output. Gain is set by external resistors

11

MIC

Microphone amplifier input. Bias voltage is approximately V

B

12

MUTE

Mute input. A logic low (< 0.8V) sets normal operation. A logic high (> 2V) mutes the microphone

amplifier without affecting the rest of the circuit. Input impedance is nominally 90 k

Ω

13

VCI

14

CT

Response time. An RC at this pin sets the response time for the circuit to switch modes