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U4082B-MFLG Datasheet(PDF) 9 Page - ATMEL Corporation |
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U4082B-MFLG Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 30 page 9 4743D–CORD–03/06 U4082B 3.10 Summary of the Truth Table • The circuit will switch to transmit if - both transmit level detectors sense higher signal levels relative to the respective receive level detectors (TLI1 versus RLI1, TLI2 versus RLI2), and - the transmit background noise monitor indicates the presence of speech. • The circuit will switch to receive if - both receive level detectors sense higher signal levels relative to the respective transmit level detectors, and - the receive background noise monitor indicates the presence of speech. • The circuit will switch to fast idle mode if the level detectors disagree on the relative strengths of the signal levels, and at least one of the background noise monitors indicates speech. For example, referring to the block diagram (Figure 1-2 on page 2), if there is a sufficient signal at the microphone amp output (TLI2) to override the speaker signal (RLI2) and there is sufficient signal at the receive input (RLI1) to override the signal at the hybrid output (TLI1), and either or both background monitors indicate speech, then the circuit will be in fast idle mode. Two conditions that can cause fast idle mode: - when both talkers are attempting to gain control of the system by talking at the same time, and - when one talker is in a very noisy environment, forcing the other talker to continually override that noise level. In general, fast idle mode will occur infrequently. • The circuit will switch to slow idle mode when - both talkers are quiet (no speech present), or - when one talker's speech level is continuously overridden by noise at the other speaker's location. The time required to switch the circuit between transmit, receive, fast idle and slow idle is determined in part by the components at pin 14 (see the section on switching times for a more complete explanation of the switching time components). A diagram of the C T circuitry is shown in Figure 3-4, and operates as follows: Figure 3-4. C T Attenuator Control Block Circuit I 2 Attenuator control - + 2 k Ω 15 14 Volume control Dial tone detector AGC 60 µA To attenuators 4 C1 to C4 I 1 V B R T C T C T |
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