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AT572D940HF-CJ Datasheet(PDF) 33 Page - ATMEL Corporation

Part # AT572D940HF-CJ
Description  DIOPSIS 940HF ARM926EJ-S PLUS ONE GFLOPS DSP
Download  39 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT572D940HF-CJ Datasheet(HTML) 33 Page - ATMEL Corporation

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7010AS–DSP–07/07
AT572D940HF Preliminary
Each TWI interconnects components on a unique two-wire bus, made of one clock line and one
data line which speeds of up to 400 Kbits per second, based on a byte oriented transfer format.
Each TWI is programmable as a master with sequential or single-byte access.
A configurable baud rate generator allows the output data rate to be adapted to a wide range of
core clock frequencies.
5.11.10
Universal Synchronous Asynchronous Rx Tx (USART)
The D940HF provides three independent USARTs.
Each USART features:
• Synchronous and Asynchronous mode
• Programmable Baud Rate Generator (up to 115.2 Kbps in Asynchronous Mode and system
clock frequency in Synchronous Mode)
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
• IrDA modulation and demodulation
• PDC connection
5.11.11
Serial Synchronous Controller (SSC)
The D940HF provides four independent SSCs.
Each SSC provides a programmable serial synchronous communication link to be used in audio
and telecom applications (CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card
Reader, SPI, ...).
The PDC connection allows a direct data transfer between the CODECs and mAgicV data mem-
ory, ARM internal memory or external memories.
5.11.12
Serial Peripheral Interface (SPI)
The D940HF provides two independent SPIs.
Each SPI supports the communication with serial external devices such as DataFlash, ADCs,
DACs, LCD Controllers, CAN Controllers and Sensors.
Four chip selects with external decoder support allow communication with up to 15 peripherals.
The PDC connection allows a direct data transfer between these serial devices and mAgicV
data memory, ARM internal memory or external memories.
5.11.13
Debug Unit (DBGU)
The DBGU is a 2-wire UART dedicated to Debug Communication.
The DBGU TX and RX channels are associated with two PDC channels.
The Debug Unit also generates the Debug Communication Channel (DCC) signals provided by
the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the
status of the DCC read and write registers and generate an interrupt to the ARM processor,
allowing the handling of the DCC under interrupt control.


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