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AT572D940HF-CJ Datasheet(PDF) 32 Page - ATMEL Corporation |
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AT572D940HF-CJ Datasheet(HTML) 32 Page - ATMEL Corporation |
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32 / 39 page  32 7010AS–DSP–07/07 AT572D940HF Preliminary • 8-level Priority Controller • Fast Forcing: allows redirection of any normal interrupt source on the nFIQ 5.11.6 Parallel Input/Output (PIO) The three PIOs provide globally 96 programmable I/O Lines. These lines are fully programmable through Set/Clear Registers or linked to one of the two peripheral functions. Each I/O Line (assigned to a peripheral or used as a general purpose I/O) provides: • Input change interrupt • Glitch filter • Multi-drive option enables driving in open drain • Programmable pull up on each I/O line • Pin data status register, supplies visibility of the level on the pin at any time 5.11.7 Universal Synchronous Bus Device (USBD) The USB Device provides communication services between an external host and D940HF. The USB device is connected to the APB through a FIFO. The USB Device features: • USB V2.0 full-speed compliant, 12 Mbits per second • Embedded USB V2.0 full-speed transceiver • Embedded dual-port RAM for endpoints • Suspend/Resume logic • Embedded Transceivers 5.11.8 Timer Counter (TC) The TC consists of three 16-bit Timer Counter Channels providing a wide range of functions including: • Frequency Measurement • Event Counting • Interval Measurement • Pulse Generation •Delay Timing • Pulse Width Modulation • Up/down Capabilities Each channel is user-configurable and contains: • Three external clock inputs • Five internal clock inputs • Two multi-purpose input/output signals 5.11.9 Two Wire Interface (TWI) The D940HF provides two independent TWIs. |
Similar Part No. - AT572D940HF-CJ |
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