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AT572D940HF-CJ Datasheet(PDF) 24 Page - ATMEL Corporation |
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AT572D940HF-CJ Datasheet(HTML) 24 Page - ATMEL Corporation |
24 / 39 page ![]() 24 7010AS–DSP–07/07 AT572D940HF Preliminary 5.9.1 Static Memory Controller (SMC) The SMC gives to the AHB enabled Hosts the capability to access to the following type of exter- nal memories: SRAM, Nor-Flash, EPROM, EEPROM. The additional NAND LOGIC also provides the SMC with the capability to interface the Smart- Media removable non-volatile memory cards and the Nand FLASH memory chips. The additional Compact Flash logic provides the SMC with the capability to interface the Com- pact Flash removable non-volatile memory cards. 5.9.2 Synchronous Dynamic RAM Controller (SDRAMC) The SDRAMC provides the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAMC supports a read or write burst length of one location. It does not support byte read/write bursts or half-word write bursts. It keeps track of the active row in each bank (avoiding precharge and active when, changing bank, the old row is accessed), thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So it is advisable to avoid accessing different rows in the same bank in order to optimize performance. The maximum number of SDRAM locations that can be randomly accessed without penalty cycles (precharge, active) corresponds to the device row size x the number of banks. The SDRAMC can support row size up to 2048 locations and 4 banks: hence maximum 8K locations can be accessed without penalties. Anyway, typical SDRAM row size are 512/256 locations so maximum 2K/1K locations can be accessed without penalties. 5.10 Memory Mapping The present section describes the memory mapping of ARM9System. Table 5-1 shows the D940HF global memory map: Table 5-1. D940HF Global Memory Map Start Address Size (MB) masters ARM9-I mst # 0 ARM9-D mst #1 PDC mst # 2 magicV mst # 3 USB mst # 4 ETH mst # 5 m-JTAG mst # 6 0x0000 0000 256 Internal Memories (See Table 5-3) 0x1000 0000 8 x 256 External Memories (See Table 5-2) 0x9000 0000 6 x 256 Undefined (Abort) 0xF000 0000 256 Internal Peripherals (See Table 5-4) |
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