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AT572D940HF-CJ Datasheet(PDF) 23 Page - ATMEL Corporation |
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AT572D940HF-CJ Datasheet(HTML) 23 Page - ATMEL Corporation |
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23 / 39 page  23 7010AS–DSP–07/07 AT572D940HF Preliminary – Compliance with Open HCI Rev 1.0 specification – Compliance with USB V2.0 Full-speed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices – Root hub integrated with two downstream USB ports – Two embedded USB transceivers 5.7 Ethernet MAC 10/100 The Ethernet MAC acting as an AHB master controls the data exchange between the ethernet channel and the ARM Internal RAM or the external memories. The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3u data frame format. The Eth- ernet MAC contains the required logic and transmits and receives FIFOs for the DMA management. In addition, it is interfaced through MDIO/MDC pins for the PHY layer manage- ment. The Ethernet MAC can transfer data through the Reduced Media Independent Interface (RMII). The aim of the interface reduction is to lower the pin count for a switch product that can be con- nected to multiple PHY interfaces. The characteristics specific to RMII mode are: • Single clock at 50 MHz frequency • Reduction of required control pins • Reduction of data paths to di-bit (2-bit wide) by doubling clock frequency • 10 Mbits/sec. and 100 Mbits/sec. data capability 5.8 mAgicV JTAG The mAgicV-JTAG provides the JTAG interface to the mAgicV core. It converts JTAG com- mands coming from a JTAG probe into AHB cycles. Acting as an AHB master it can access all mAgicV memories and registers, thus allowing mAgicV debug software to control the core and its resources: to upload/download data and programs and to configure functional and debug registers. 5.9 External Bus Interface (EBI) Each enabled AHB master can access the external memory resources through the EBI. The External Bus IF incorporates the Static Memory Controller (SMC) and Synchronous Dynamic RAM controller (SDRAMC). The EBI features: • Eight Chip Select Lines (four via PIO lines) • 26-bit Address Bus (four msb via PIO lines) • 32-bit Data Bus • Multiple Access Modes supported • Byte Write Lines • Programmable Wait State Generation • Programmable Data Float Time • Slow clock mode supported |
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