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AT572D940HF-CJ Datasheet(PDF) 22 Page - ATMEL Corporation |
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AT572D940HF-CJ Datasheet(HTML) 22 Page - ATMEL Corporation |
22 / 39 page ![]() 22 7010AS–DSP–07/07 AT572D940HF Preliminary 5.4.2.1 BMS = 1, Boot on Embedded ROM The system boots using the Boot Program from the embedded ROM following the steps listed below: Checks the presence of an SD card with a boot.bin file in the main dir: If the file is found: • Downloads the code in internal SRAM at 0x300000 • Executes Remap command • Runs SD Boot code If the file is not found, downloads the code from the SPI DataFlash ®: • Downloads the code in internal SRAM at 0x300000 • Checks the presence of a valid code on the first six word • Executes Remap command • Runs DataFlash Boot code In case no valid program is detected in the external SPI DataFlash: – Activates a Boot uploader enabling small monitor functionalities (read/write/run) interface with the SAM-BA ™ application – Performs an automatic detection of the communication link: Serial communication on a DBGU (XModem protocol) USB Device Port (CDC Protocol) 5.4.2.2 BMS = 0, Boot on External Memory • Boot on slow clock (32,768 Hz) • Boot with the default configuration for the Static Memory Controller, byte select mode, 32-bit data bus, Read/Write controlled by Chip Select, allows boot on 32-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock Peripheral Data Controller (PDC). 4. Switch the main clock to the new value. 5.5 Peripheral Data Controller (PDC) The PDC acting as an AHB master controls the data transfer between on chip peripherals: USARTs, SPIs, SSCs, MCI, DBGU, TWIs and the on- and off-chip memories. This leaves both the processors free of the overhead related to this function. 5.6 USB Host The USB host acting as an AHB master controls the data exchange between the two USB host channels (port A and port B) and the ARM Internal RAM or the external memories. The USB Host Port features: |
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