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AT572D940HF-CJ Datasheet(PDF) 21 Page - ATMEL Corporation |
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AT572D940HF-CJ Datasheet(HTML) 21 Page - ATMEL Corporation |
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21 / 39 page  21 7010AS–DSP–07/07 AT572D940HF Preliminary 5.4 ARM926 Processor The ARM926 is a member of ARM9 ™ family of general purpose microprocessors. The ARM926 is targeted at multi-tasking applications where full memory management, high performance and low power are important. The ARM926 supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. The ARM926 includes features for efficient execution of Java byte codes. The ARM926 supports the ARM debug architecture and includes logic to assist both the hard- ware and the software debug. The ARM926 provides an integer core that supports the DSP instruction set extension. The ARM926 supports virtual memory addressing through its standard ARM v4 and v5 memory management unit (MMU). The ARM926 provides two independent AHB master interfaces for data and instruction. The ARM926 provides two independent Tightly Coupled Memory (TCM) interfaces. The ARM926 implements ARM architecture version 5TEJ with 5 stage pipeline. The ARM926 embeds 16-Kbyte Data Cache and 16-Kbyte Instruction Cache. 5.4.1 ARM Memories The ARM926 memories consist of: • 32Kbyte ROM selectable as boot memory • 48Kbyte Fast SRAM – Single Cycle Access at full bus speed – Supports ARM926EJ-S TCM interface at full processor speed – D-TCM and I-TCM programmable size 5.4.2 Arm Boot The system always boots at address 0x0. The memory layout can be configured with two param- eters to ensure a maximum number of possibilities for booting. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix. When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user, at ones convenience, to lay out the ROM or an exter- nal memory to 0x0. This is done via hardware at reset. Note that Memory blocks not affected by these parameters can always be seen at their specified base addresses. The complete memory map is presented in Table 5-1 to Table 5-4. The Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. |
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