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AT572D940HF-CJ Datasheet(PDF) 18 Page - ATMEL Corporation |
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AT572D940HF-CJ Datasheet(HTML) 18 Page - ATMEL Corporation |
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18 / 39 page  18 7010AS–DSP–07/07 AT572D940HF Preliminary can also be used to perform 16-bit signed integer arithmetic operations in parallel with the activ- ities of the operators block (40-bit floating point and 32 signed integer operations). The MAGU also performs the loop control computations needed to verify if the end of a loop is reached. 5.3.6 Flow Controller The Flow Controller is dedicated to program address generation, conditioning, predication and software pipelining of systematic loops. The Program Address Generation Unit is devoted to control the correct Program Counter generation according to the program flow. It generates addresses for linear code execution as well as for non-sequential program flow. The Condition Generation Unit combines the flags generated by the operators and by the MAGU to produce complex conditions flags used to control the program execution. The Program Address Genera- tion Unit also allows to perform conditioned and unconditioned branch instructions, loops, call to subroutines and return from subroutines. 5.3.7 Dual-Port On-Chip Program Memory The Program Memory stores the VLIW program to be executed by mAgicV. It is 8K words by 128-bit dual port memory. One port is driven by the Flow Controller to fetch the compressed VLIW word. The other port is accessed by the DMA engine, supported by the AHB master inter- face, or by the external devices through mAgicV AHB slave port. 5.3.8 5 predicated VLIW Issues At every cycle, a typical mAgicV VLIW instruction activates 5 issues named AGU0, AGU1, ADD, MULT and FLOW. The first two issues are associated to the pair of independent Address Gener- ation Units in the MAGU. The third issue drives the Arithmetic Add/Subtract section of the Operators Block, the fourth drives the Multiplier section, and the last issue drives the Flow Con- troller. Each issue is predicated by a specific predication field, for conditional execution without pipeline breaking penalties. Using different instruction formats, the VLIW word can also contain initialization requests for the DMA engine, single cycle loading of multiple immediate values and other service instructions. 5.3.9 Software pipelining Software pipelining of systematic loops is optimally supported by a dedicated engine which acti- vates the VLIW issues only during the appropriate loop iterations. This mechanism is designed to reach optimal program memory usage of the DSP library and completes the general purpose Code Compression scheme. 5.3.10 Program Compression The mAgicV VLIW architecture is natively designed for optimal program density. Moreover, a program compression scheme allows an average additional program compression between 2 and 3. Therefore, more than 10 issues are stored for each 128 bit program memory locations. A high Program Memory density is achieved thanks to the combined effect of Program Compres- sion and Software Pipelining. The DSP side of many applications can be implemented on the D940HF using only the internal memory. In fact, the 8K by 128-bit program memory size pro- vides, with code compression, ~50K DSP assembler instructions stored on-chip (typical). For DSP libraries, the density is even greater where software pipelining is activated. If the on-chip program memory is not large enough to contain the full DSP application, a DMA must be launched to refill the dual-port Program Memory. Thanks to the program compression, the pro- gram memory refill does not stall the activities of the DSP core. |
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