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AT572D940HF-CJ Datasheet(PDF) 16 Page - ATMEL Corporation |
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AT572D940HF-CJ Datasheet(HTML) 16 Page - ATMEL Corporation |
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16 / 39 page  16 7010AS–DSP–07/07 AT572D940HF Preliminary 5.3 mAgicV VLIW DSP Processor The mAgicV VLIW DSP is the numeric processor of the D940HF. It operates on IEEE 754 40-bit extended precision floating-point and 32-bit integer numeric format. The main components of the DSP subsystem are the core processor, the on-chip memories, the DMA engine and its AHB master and slave interfaces. The operators block, the register file, the multiple address genera- tion unit and the program decoding and sequencing unit are the computing part of the core processor. A short description of each block is given in the following paragraphs. Figure 5-1. mAgicV DSP Block Diagram 5.3.1 RISC-like VLIW DSP mAgicV is a Very Long Instruction Word engine, but from an user point of view, it works like a RISC machine by implementing triadic computing operations on data coming from the register file, and data move operations between the local memories and the register file. The operators are pipelined for maximum performance. The pipeline depth depends on the operator used. The scheduling and parallelism operations are automatically defined and managed at compile time by the assembler-optimizer, allowing efficient code execution. The architecture is designed for efficient C-language support. 5.3.2 16-port, 256x40-bit Data Register File System In order to provide optimal data bandwidth and to give the best support to the RISC-like pro- gramming model, mAgicV arithmetic computations are supported by a 16-ported, 256x40-bit entries, Data Register File System. The Data Register File can also be viewed as a complex 128-entry register file. It can be used as a complex register file (real + imaginary part), or as a dual register file for vectorial operations. When performing scalar instructions on the real domain, the register file can be used as an ordinary 256 register file. Both the odd and even sides of the register file are 9-ported (4-read ports and 4-write ports for computing/move opera- tions + 1 port for independent debug access), making a total of 16 I/O ports available for the data AHB Master DMA Engine 4-address/cycle Multiple DSP Address Generation Unit 16 multi-field Address Register File Operators: 10-float ops/cycle 16-port 256x40-bit Data Register File System 2-port, 8Kx128-bit, VLIW Program Memory Flow Controller, VLIW Decoder Instruction Decoder Condition Generation Status Register Program Counter VLIW Decompressor 6-access/cycle Data Memory System 16Kx40-bit AHB Slave, e.g. DMA Target AHB layer-x Multi Layer AHB System Bus AHB layer-y |
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