6

5203AS–CRYPT–7/08

AT88SC0404CA

7.2

Memory Reset

After an interruption in communication due protocol errors, power loss or any reason,

perform

"Acknowledge Polling" to properly recover from the condition. Acknowledge polling consists of

sending a start condition followed by a valid CryptoMemory command byte and determining if

the device responded with an ACKNOWLEDGE.

Figure 7-1.

Bus Time for 2-Wire Serial Communications. SCL: Serial Clock, SDA: Serial Data I/O

Figure 7-2.

Write Cycle Timing. SCL: Serial Clock, SDA: Serial Data I/O

Note:

The Write Cycle time twr is the time from a valid stop condition of a write sequence to the end of

the internal clear/write cycle.

Figure 7-3.

Data Validity

t

WR

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

DATA

CHANGE

ALLOWED