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AT88SC0404CA-SU Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT88SC0404CA-SU Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 20 page ![]() 5 5203AS–CRYPT–7/08 AT88SC0404CA 7. Device Operations for Synchronous Protocols 7.1 Clock and Data Transitions The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 7-3 on page 6). Data changes during SCL high periods will indicate a start or stop condition as defined below. 7.1.1 Start Condition A high-to-low transition of SDA with SCL high defines a START condition which must precede all commands (see Figure 7-4 on page 7). 7.1.2 Stop Condition A low-to-high transition of SDA with SCL high defines a STOP condition. After a read sequence, the STOP condition will place the EEPROM in a standby power mode (see Figure 7-4 on page 7). 7.1.3 ACKNOWLEDGE All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens dur- ing the ninth clock cycle (see Figure 7-5 on page 7). Table 6-2. AC Characteristics Applicable over recommended operating range from V CC = +2.7 to 3.6V, TAC = -40°C to +85°C, CL = 30pF (unless otherwise noted) Parameter Min Max Units f CLK Async Clock Frequency 1 4 MHz f CLK Synch Clock Frequency 0 1 MHz Clock Duty cycle 40 60 % t R “Rise Time - SDA/IO, RST” 1 uS tF “Fall Time - SDA/IO, RST” 1 uS tR Rise Time - SCL/CLK 9% x period uS t F Fall Time - SCL/CLK 9% x period uS tAA Clock Low to Data Out Valid 250 nS tHD.STA Start Hold Time 200 nS t SU.STA Start Set-up Time 200 nS tHD.DAT Data In Hold Time 10 nS tSU.DAT Data In Set-up Time 100 nS t SU.STO Stop Set-up Time 200 nS tDH Data Out Hold Time 20 nS tWR Write Cycle Time 5mS |
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