3

5200AS–CRYPT–7/08

AT88SC0104CA

Figure 4-1.

Block Diagram

5.

Pin Descriptions

5.1

Supply Voltage (VCC)

5.2

Clock (SCL/CLK)

When using the asynchronous T = 0 protocol, the CLK (SCL) input provides the device with a

carrier frequency

f. The nominal length of one bit emitted on I/O is defined as an “elementary

time unit” (ETU) and is equal to 372/

f.

When using the synchronous protocol, data clocking is done on the positive edge of the clock

when writing to the device and on the negative edge of the clock when reading from the device.

5.3

Reset (RST)

The AT88SC0104CA provides an ISO 7816-3 compliant asynchronous Answer-To-Reset (ATR)

sequence. Upon activation of the reset sequence, the device outputs bytes contained in the 64-

bit Answer-To-Reset register. An internal pull-up on the RST input pad allows the device to oper-

ate in synchronous mode without bonding RST. The AT88SC0104CA does not support an

Answer-To-Reset sequence in the synchronous mode of operation.

5.4

Serial Data (SDA/IO)

The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be

wired with any number of other open-drain or open-collector devices. An external pull-up resistor

itance loading the SDA/IO bus will determine the rise time of SDA/IO. This rise time will

determine the maximum frequency during read operations. Low value pull-up resistors will allow

higher frequency operations while drawing higher average power supply current. SDA/IO infor-

mation applies to both asynchronous and synchronous protocols.

Random

Generator

Authentication,

Encryption and

Certification Unit

EEPROM

Answer to Reset

Data Transfer

Password

Verification

Reset Block

Asynchronous

ISO Interface

Synchronous

Interface

Power

Management

VCC

GND

SCL/CLK

SDA/IO

RST