14

5200AS–CRYPT–7/08

AT88SC0104CA

Once synchronous mode has been selected, it is not possible to switch to asynchronous mode

without first powering off the device.

Figure 13-1. Synchronous 2-Wire Protocol

Note:

Five clock pulses must be sent before the first command is issued.

13.2

Asynchronous T = 0 Protocol

This power-up sequence complies to ISO 7816-3 for a cold reset in smart card applications.

V

Set I/O (SDA) in receive mode.

Provide a clock signal to CLK (SCL).

RST goes high after 400 clock cycles.

The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory

density within the CryptoMemory family.

Once asynchronous mode has been selected, it is not possible to switch to synchronous mode

without first powering off the device.

Figure 13-2. Asynchronous T = 0 Protocol (Gemplus Patent)

14. Initial Device Programming

Enabling the security features of CryptoMemory requires prior personalization. Personalization

entails setting up of desired access rights by zones, passwords and key values, programming

these values into the configuration memory with verification using simple WRITE and READ

commands, and then blowing fuses to lock this information in place.

Gaining access to the configuration memory requires successful presentation of a secure (or

transport) code. The initial signature of the secure (transport) code for the AT88SC0104CA

Vcc

I/O-SDA

RST

CLK-SCL

1

2

3

45

Vcc

I/O-SDA

RST

CLK-SCL

ATR