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MPC8610EC Datasheet(PDF) 1 Page - Freescale Semiconductor, Inc |
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MPC8610EC Datasheet(HTML) 1 Page - Freescale Semiconductor, Inc |
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1 / 96 page  Freescale Semiconductor Data Sheet Document Number: MPC8610EC Rev. 0, 10/2008 © Freescale Semiconductor, Inc., 2008. All rights reserved. Features • High-performance, 32-bit e600 core, that implements the Power Architecture™ technology – Eleven execution units and three register files – Two separate 32-Kbyte instruction and data level 1 (L1) caches – Integrated 256-Kbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC – 36-bit real addressing – Multiprocessing support features – Power and thermal management • MPX coherency module (MCM) • Address translation and mapping units (ATMUs) • DDR/DDR2 memory controller – 64- or 32-bit data path (72-bit with ECC) – Up to 533-MHz DDR2 data rate and up to 400 MHz DDR data rate – Up to 16 Gbytes memory • Enhanced local bus controller (eLBC) – Operating at up to 133 MHz – Eight chip selects • Display interface unit – Maximum display resolution: 1280 ×1024 – Maximum display refresh rate: 60 Hz – Display color depth: up to 24 bpp – Display interface: parallel TTL • OpenPIC-compliant programmable interrupt controller (PIC) – Supports 16 programmable interrupt and processor task priority levels – Supports 12 discrete external interrupts and 48 internal interrupts – Eight global high resolution timers/counters that can generate interrupts – Support for PCI Express message-shared interrupts (MSIs) •Dual I 2C controllers – Master or slave I 2C mode support – Boot sequencer – Optionally loads configuration data from serial ROM at reset via I 2C interface – Can be used to initialize configuration registers and/or memory – Supports extended I 2C addressing mode • DUART • Fast InfraRed interface • Serial peripheral interface – Master or slave support • Dual integrated four-channel DMA controllers – All channels accessible by both local and remote masters – Supports transfers to or from any local memory or I/O port – Ability to start and flow control each DMA channel from external 3-pin interface • Watchdog timer • Dual global timer modules • 32-bit PCI interface, 33 or 66 MHz bus frequency • Dual PCI Express® controllers – PCI Express 1.0a compatible – PCI Express controller 1 supports x1, x2, and x4 link widths; PCI Express controller 2 supports x1, x2, x4, and x8 link widths – 2.5 Gbaud, 2.0 Gbps lane • Device performance monitor – Supports eight 32-bit counters that count the occurrence of selected events – Ability to count up to 512 counter-specific events – Supports 64 reference events that can be counted on any of the 8 counters – Supports duration and quantity threshold counting – Burstiness feature that permits counting of burst events with a programmable time between bursts – Triggering and chaining capability – Ability to generate an interrupt on overflow • IEEE Std 1149.1™ compliant, JTAG boundary scan • Available as 783-pin, flip-chip, plastic ball grid array (FC-PBGA) MPC8610 Integrated Host Processor Hardware Specifications |
Similar Part No. - MPC8610EC |
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Similar Description - MPC8610EC |
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