TPS650250

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I

This pin must be connected to a resistor divider between VDCDC3 and GND. The output voltage of the

DEFDCDC3

32

DCDC3 converter can be set in a range from 0.6V to VINDCDC3.

EN_DCDC1

20

I

VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.

EN_DCDC2

19

I

VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.

EN_DCDC3

18

I

VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.

LDO REGULATOR SECTION

VINLDO

15

I

Input voltage for LDO1 and LDO2

VLDO1

16

O

Output voltage of LDO1

VLDO2

14

O

Output voltage of LDO2

EN_LDO

17

I

Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs

EN_Vdd_alive

24

I

Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO

Vdd_alive

12

O

Output voltage for Vdd_alive

FB_LDO1

11

I

Feedback pin for LDO1

FB_LDO2

10

I

Feedback pin for LDO2

CONTROL AND I2C SECTION

Select between Power Safe Mode and forced PWM Mode for DCDC1, DCDC2 and DCDC3. In Power Safe

MODE

23

I

Mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is

selected. If Pin has low level, then Device operates in Power Safe Mode.

PWRFAIL

21

O

Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.

PWRFAIL_SNS

30

I

Input for the comparator driving the /PWRFAIL output

10

Submit Documentation Feedback

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): TPS650250