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HD6432126R Datasheet(PDF) 17 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 17 Page - Renesas Technology Corp |
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17 / 843 page  viii 12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions].............................................................................. 291 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]...................... 292 12.2.13 Module Stop Control Register (MSTPCR) ........................................................... 293 12.3 Operation ............................................................................................................................ 294 12.3.1 TCNT Incrementation Timing .............................................................................. 294 12.3.2 Compare-Match Timing........................................................................................ 295 12.3.3 TCNT External Reset Timing ............................................................................... 297 12.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 297 12.3.5 Operation with Cascaded Connection ................................................................... 298 12.3.6 Input Capture Operation........................................................................................ 299 12.4 Interrupt Sources ................................................................................................................ 301 12.5 8-Bit Timer Application Example...................................................................................... 302 12.6 Usage Notes........................................................................................................................ 302 12.6.1 Contention between TCNT Write and Clear......................................................... 303 12.6.2 Contention between TCNT Write and Increment ................................................. 304 12.6.3 Contention between TCOR Write and Compare-Match ....................................... 305 12.6.4 Contention between Compare-Matches A and B.................................................. 306 12.6.5 Switching of Internal Clocks and TCNT Operation.............................................. 306 Section 13 Timer Connection [H8S/2128 Series] ....................................................... 309 13.1 Overview ............................................................................................................................ 309 13.1.1 Features ................................................................................................................. 309 13.1.2 Block Diagram ...................................................................................................... 310 13.1.3 Input and Output Pins............................................................................................ 311 13.1.4 Register Configuration .......................................................................................... 312 13.2 Register Descriptions.......................................................................................................... 312 13.2.1 Timer Connection Register I (TCONRI) .............................................................. 312 13.2.2 Timer Connection Register O (TCONRO) ........................................................... 314 13.2.3 Timer Connection Register S (TCONRS) ............................................................ 316 13.2.4 Edge Sense Register (SEDGR) ............................................................................. 319 13.2.5 Module Stop Control Register (MSTPCR) ........................................................... 321 13.3 Operation ............................................................................................................................ 322 13.3.1 PWM Decoding (PDC Signal Generation) ........................................................... 322 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ...................... 324 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period ..................................... 325 13.3.4 IHI Signal and 2fH Modification .......................................................................... 327 13.3.5 IVI Signal Fall Modification and IHI Synchronization ........................................ 329 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)....................................................................... 330 13.3.7 HSYNCO Output .................................................................................................. 333 13.3.8 VSYNCO Output .................................................................................................. 334 13.3.9 CBLANK Output .................................................................................................. 335 |
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