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HD6432126R Datasheet(PDF) 26 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 26 Page - Renesas Technology Corp |
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26 / 843 page  2 Table 1.1 Overview Item Specifications CPU • General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for real-time control Maximum operating frequency: 20 MHz/5 V, 10 MHz/3 V High-speed arithmetic and logic operations 8/16/32-bit register-register add/subtract: 50 ns (20 MHz operation) 16 × 16-bit register-register multiply: 1000 ns (20 MHz operation) 32 ÷ 16-bit register-register divide: 1000 ns (20 MHz operation) • Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit transfer/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions • Two CPU operating modes Normal mode: 64-kbyte address space Advanced mode: 16-Mbyte address space Operating modes • Three MCU operating modes External Data Bus Mode CPU Operating Mode Description On-Chip ROM Initial Value Maximum Value 1 Normal Expanded mode with on-chip ROM disabled Disabled 8 bits 8 bits 2 Advanced Expanded mode with on-chip ROM enabled Enabled 8 bits 8 bits Single-chip mode None 3 Normal Expanded mode with on-chip ROM enabled Enabled 8 bits 8 bits Single-chip mode None Bus controller • 2-state or 3-state access space can be designated for external expansion areas • Number of program wait states can be set for external expansion areas |
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