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HD6432126R Datasheet(PDF) 18 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 843 page  ix Section 14 Watchdog Timer (WDT)............................................................................... 337 14.1 Overview ............................................................................................................................ 337 14.1.1 Features ................................................................................................................. 337 14.1.2 Block Diagram ...................................................................................................... 338 14.1.3 Pin Configuration .................................................................................................. 339 14.1.4 Register Configuration .......................................................................................... 340 14.2 Register Descriptions.......................................................................................................... 340 14.2.1 Timer Counter (TCNT) ......................................................................................... 340 14.2.2 Timer Control/Status Register (TCSR) ................................................................. 341 14.2.3 System Control Register (SYSCR) ....................................................................... 344 14.2.4 Notes on Register Access...................................................................................... 345 14.3 Operation ............................................................................................................................ 346 14.3.1 Watchdog Timer Operation................................................................................... 346 14.3.2 Interval Timer Operation ...................................................................................... 347 14.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 348 14.4 Interrupts ............................................................................................................................ 348 14.5 Usage Notes........................................................................................................................ 349 14.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 349 14.5.2 Changing Value of CKS2 to CKS0....................................................................... 349 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode ................ 349 14.5.4 Counter Value in Transitions between High-Speed Mode, Subactive Mode, and Watch Mode .......................................................................................................... 350 14.5.5 OVF Flag Clear Condition .................................................................................... 350 Section 15 Serial Communication Interface (SCI) ..................................................... 351 15.1 Overview ............................................................................................................................ 351 15.1.1 Features ................................................................................................................. 351 15.1.2 Block Diagram ...................................................................................................... 353 15.1.3 Pin Configuration .................................................................................................. 353 15.1.4 Register Configuration .......................................................................................... 354 15.2 Register Descriptions.......................................................................................................... 355 15.2.1 Receive Shift Register (RSR)................................................................................ 355 15.2.2 Receive Data Register (RDR) ............................................................................... 355 15.2.3 Transmit Shift Register (TSR) .............................................................................. 356 15.2.4 Transmit Data Register (TDR).............................................................................. 356 15.2.5 Serial Mode Register (SMR)................................................................................. 357 15.2.6 Serial Control Register (SCR)............................................................................... 359 15.2.7 Serial Status Register (SSR).................................................................................. 363 15.2.8 Bit Rate Register (BRR)........................................................................................ 367 15.2.9 Serial Interface Mode Register (SCMR) ............................................................... 375 15.2.10 Module Stop Control Register (MSTPCR) ........................................................... 376 15.3 Operation ............................................................................................................................ 377 15.3.1 Overview ............................................................................................................... 377 |
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