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HD6432126R Datasheet(PDF) 13 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 843 page  iv 6.2.2 Wait State Control Register (WSCR).................................................................... 135 6.3 Overview of Bus Control.................................................................................................... 137 6.3.1 Bus Specifications ................................................................................................. 137 6.3.2 Advanced Mode .................................................................................................... 138 6.3.3 Normal Mode ........................................................................................................ 138 6.3.4 I/O Select Signal.................................................................................................... 138 6.4 Basic Bus Interface............................................................................................................. 139 6.4.1 Overview ............................................................................................................... 139 6.4.2 Data Size and Data Alignment.............................................................................. 139 6.4.3 Valid Strobes ......................................................................................................... 141 6.4.4 Basic Timing ......................................................................................................... 142 6.4.5 Wait Control.......................................................................................................... 144 6.5 Burst ROM Interface .......................................................................................................... 146 6.5.1 Overview ............................................................................................................... 146 6.5.2 Basic Timing ......................................................................................................... 146 6.5.3 Wait Control.......................................................................................................... 147 6.6 Idle Cycle............................................................................................................................ 148 6.6.1 Operation ............................................................................................................... 148 6.6.2 Pin States in Idle Cycle ......................................................................................... 149 6.7 Bus Arbitration ................................................................................................................... 149 6.7.1 Overview ............................................................................................................... 149 6.7.2 Operation ............................................................................................................... 149 6.7.3 Bus Transfer Timing ............................................................................................. 150 Section 7 Data Transfer Controller [H8S/2128 Series] ............................................. 151 7.1 Overview ............................................................................................................................ 151 7.1.1 Features ................................................................................................................. 151 7.1.2 Block Diagram ...................................................................................................... 152 7.1.3 Register Configuration .......................................................................................... 153 7.2 Register Descriptions.......................................................................................................... 154 7.2.1 DTC Mode Register A (MRA).............................................................................. 154 7.2.2 DTC Mode Register B (MRB).............................................................................. 156 7.2.3 DTC Source Address Register (SAR) ................................................................... 157 7.2.4 DTC Destination Address Register (DAR) ........................................................... 157 7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 157 7.2.6 DTC Transfer Count Register B (CRB)................................................................ 158 7.2.7 DTC Enable Registers (DTCER) .......................................................................... 158 7.2.8 DTC Vector Register (DTVECR) ......................................................................... 159 7.2.9 Module Stop Control Register (MSTPCR) ........................................................... 160 7.3 Operation ............................................................................................................................ 161 7.3.1 Overview ............................................................................................................... 161 7.3.2 Activation Sources ................................................................................................ 163 7.3.3 DTC Vector Table ................................................................................................. 164 |
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