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HD6432126R Datasheet(PDF) 12 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 12 Page - Renesas Technology Corp |
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12 / 843 page  iii 5.1.2 Block Diagram ...................................................................................................... 100 5.1.3 Pin Configuration .................................................................................................. 100 5.1.4 Register Configuration .......................................................................................... 101 5.2 Register Descriptions.......................................................................................................... 101 5.2.1 System Control Register (SYSCR) ....................................................................... 101 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC) ............................................ 102 5.2.3 IRQ Enable Register (IER) ................................................................................... 103 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 104 5.2.5 IRQ Status Register (ISR) ..................................................................................... 105 5.2.6 Address Break Control Register (ABRKCR)........................................................ 106 5.2.7 Break Address Registers A, B, C (BARA, BARB, BARC).................................. 107 5.3 Interrupt Sources ................................................................................................................ 108 5.3.1 External Interrupts................................................................................................. 108 5.3.2 Internal Interrupts.................................................................................................. 109 5.3.3 Interrupt Exception Vector Table.......................................................................... 109 5.4 Address Breaks ................................................................................................................... 112 5.4.1 Features ................................................................................................................. 112 5.4.2 Block Diagram ...................................................................................................... 112 5.4.3 Operation ............................................................................................................... 113 5.4.4 Usage Notes .......................................................................................................... 113 5.5 Interrupt Operation ............................................................................................................. 115 5.5.1 Interrupt Control Modes and Interrupt Operation ................................................. 115 5.5.2 Interrupt Control Mode 0 ...................................................................................... 118 5.5.3 Interrupt Control Mode 1 ...................................................................................... 120 5.5.4 Interrupt Exception Handling Sequence ............................................................... 123 5.5.5 Interrupt Response Times...................................................................................... 125 5.6 Usage Notes........................................................................................................................ 126 5.6.1 Contention between Interrupt Generation and Disabling...................................... 126 5.6.2 Instructions that Disable Interrupts ....................................................................... 127 5.6.3 Interrupts during Execution of EEPMOV Instruction .......................................... 127 5.7 DTC Activation by Interrupt .............................................................................................. 128 5.7.1 Overview ............................................................................................................... 128 5.7.2 Block Diagram ...................................................................................................... 128 5.7.3 Operation ............................................................................................................... 129 Section 6 Bus Controller..................................................................................................... 131 6.1 Overview ............................................................................................................................ 131 6.1.1 Features ................................................................................................................. 131 6.1.2 Block Diagram ...................................................................................................... 132 6.1.3 Pin Configuration .................................................................................................. 133 6.1.4 Register Configuration .......................................................................................... 133 6.2 Register Descriptions.......................................................................................................... 134 6.2.1 Bus Control Register (BCR) ................................................................................. 134 |
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