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HD6432126R Datasheet(PDF) 100 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 100 Page - Renesas Technology Corp |
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100 / 843 page  76 Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode. Bit 6 IOSE Description 0 The AS/IOS pin functions as the address strobe pin (AS) (Low output when accessing an external area) (Initial value) 1 The AS/IOS pin functions as the I/O strobe pin (IOS) (Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F) Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. Bit 3 XRST Description 0 A reset is generated by watchdog timer overflow 1 A reset is generated by an external reset (Initial value) Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to on-chip supporting function registers. This bit controls CPU access to the 8-bit timer (channel X and Y) data registers and control registers (TCRX/TCRY, TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR, TCORAX, and TCORBX), and the timer connection control registers (TCONRI, TCONRO, TCONRS, and SEDGR). Bit 1 HIE Description 0 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is permitted (Initial value) 1 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is not permitted |
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Similar Description - HD6432126R |
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