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HD6432126R Datasheet(PDF) 68 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 68 Page - Renesas Technology Corp |
68 / 843 page 44 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Function Instruction Data MOV BWL BWL BWL BWL BWL BWL B BWL — BWL ———— transfer POP, PUSH ————————————— WL LDM* 3, STM*3 ————————————— L MOVFPE* 1, MOVTPE* 1 ——————— B —————— Arithmetic ADD, CMP BWL BWL ———————————— operations SUB WL BWL ———————————— ADDX, SUBX B B ———————————— ADDS, SUBS — L ———————————— INC, DEC — BWL ———————————— DAA, DAS — B ———————————— MULXU, DIVXU — BW ———————————— MULXS, DIVXS — BW ———————————— NEG — BWL ———————————— EXTU, EXTS — WL ———————————— TAS* 2 —— B ——————————— Logic operations AND, OR, XOR BWL BWL ———————————— NOT — BWL ———————————— Shift — BWL ———————————— Bit manipulation — B B — — — B B — B ———— Branch Bcc, BSR —————————— —— JMP, JSR ———————— ——— — RTS ————————————— Note: 1. Cannot be used in the H8S/2128 Series or H8S/2124 Series. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction. |
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