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HD6432126R Datasheet(PDF) 52 Page - Renesas Technology Corp |
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HD6432126R Datasheet(HTML) 52 Page - Renesas Technology Corp |
52 / 843 page 28 • High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 20 MHz 8/16/32-bit register-register add/subtract: 50 ns 8 × 8-bit register-register multiply: 600 ns 16 ÷ 8-bit register-register divide: 600 ns 16 × 16-bit register-register multiply: 1000 ns 32 ÷ 16-bit register-register divide: 1000 ns • Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states The number of execution states of the MULXU and MULXS instructions differ as follows. Number of Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 There are also differences in the address space, EXR register functions, power-down state, etc., depending on the product. |
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