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HD6432127RW Datasheet(PDF) 94 Page - Renesas Technology Corp |
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HD6432127RW Datasheet(HTML) 94 Page - Renesas Technology Corp |
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94 / 843 page  70 Bus cycle T1 T2 Unchanged Address bus AS RD WR Data bus ø High High High High impedance Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 Usage Notes 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.10.2 STM/LDM Instruction ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved /restored by one STM/LDM instruction. The following ranges can be specified in the register list. |
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