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M30620FCAFP Datasheet(PDF) 531 Page - Renesas Technology Corp |
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M30620FCAFP Datasheet(HTML) 531 Page - Renesas Technology Corp |
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531 / 615 page ![]() Controlling Power Applications Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2-214 Figure 3.7.3. Set-up procedure of controlling power using stop mode (1) Canceling protect Protect register [Address 000A16] PRCR b7 b0 1 Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled Main NOP instruction X 4 Key input interrupt request generation Initial condition b7 b0 Pull-up control register 2 [Address 03FE16] PUR2 P104 to P107 pulled high 1 Port P10 register [Address 03F416] P10 b7 b0 0 0 0 0 Key scan data Processor interrupt priority level (IPL) = 0 Interrupt enable flag (I) =0 Key input interrupt control register [Address 004D16] KUPIC Interrupt priority level select bit Set higher value than the present IPL b7 b0 1 0 0 Port P10 direction register [Address 03F616] PD10 Key scan output port Key scan input port b7 b0 1 1 1 1 0 0 0 0 Setting interrupt except stop mode cancel I nterrupt control register TBiIC(i=3 to 5) [Address 004516 to 004716] BCNIC [Address 004A16] DMiIC(i=0, 1) [Address 004B16, 004C16] ADIC [Address 004E16] SiTIC(i=0 to 2) [Address 005116, 005316, 004F16] SiRIC(i=0 to 2) [Address 005216, 005416, 005016] TAiIC(i=0 to 4) [Address 005516 to 005916] TBiIC(i=0 to 2) [Address 005A16 to 005C16] Interrupt priority level select bit 000 : Interrupt disabled b7 b0 0 0 0 Interrupt priority level select bit 000 : Interrupt disabled b7 b0 0 0 0 INTiIC(i=0 to 2) [Address 005D16 to 005F16] 0 Reserved bit Must always be set to “0” All clocks off (stop mode) System clock control register 1 [Address 000716] CM1 b7 b0 All clock stop control bit 1 : All clocks off (stop mode) 1 00 00 Reserved bit Must always be set to “0” Setting operation clock after returning from stop mode System clock control register 0 [Address 000616] CM0 XCIN-XCOUT generation Port XC select bit b7 b0 System clock select bit XCIN, XCOUT As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. 1 1 (When operating with XCIN after returning) System clock control register 0 [Address 000616] CM0 On Main clock (XIN-XOUT) stop bit b7 b0 System clock select bit XIN, XOUT As this register becomes setting mentioned above when operating with XIN (count source of BCLK is XIN), the user does not need to set it again. 00 (When operating with XIN after returning) Interrupt enable flag (I flag) “1” |
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