M30620FCAFP datasheet(525/615 Pages) RENESAS

525 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-208

DMAC Applications

3.6 Memory to Memory DMA Transfer

The following are steps for changing both source address and destination address to transfer

data from memory to another. The DMA transfer utilizes the workings that assign a higher priority

to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels. Figure

3.6.1 shows the operation timing, Figure 3.6.2 shows the block diagram, and Figures 3.6.3 and

3.6.4 show the set-up procedure.

Use the following peripheral functions:

• Timer mode of timer A

• Two DMAC channels

• One-byte temporary RAM (address 080016)

(1) Transfer the content of memory extending over 128 bytes from address A000016 to a 128-

byte area starting from address C000016. Transfer the content every time a timer A0 interrupt

request occurs.

(2) Use DMA0 for a transfer from the source to built-in memory, and DMA1 for a transfer from

built-in memory to the destination.

(1) A timer A interrupt request occurs. Though both a DMA0 transfer request and a DMA1 trans-

fer request occur simultaneously, the former is executed first.

(2) DMA0 receives a transfer request and transfers data from the source to the built-in memory.

At this time, the source address is incremented.

(3) Next, DMA1 receives a transfer request and transfers data involved from built-in memory to

the destination. At this time, the destination address is incremented.

Overview

Specifications

Operation

Figure 3.6.1. Operation timing of memory to memory DMA transfer

Timer A0

transfer request

Address bus

“0”

“1”

“0”

“1”

“0”

“1”

(1) Transfer request generation

(2) Start DMA0 transferring

(3) Start DMA1 transferring

Instruction cycle

DMA0 operation

DMA1 operation

A000016

080016

C000016

WR signal

RD signal

Source address

Destination address

Source address

Destination address

The DMA0 operation and DMA1 operation are not necessarily executed in succession

due to the a cycle steal operation.

The instruction cycle varies from instruction to instruction.

Since the parts of the RD and WR signals shown in short-dash lines vary in step with

writing to the internal RAM, waveforms are not output to the RD and WR pins.

Note 1:

Note 2:

Note 3:

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