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M30620FCAFP Datasheet(PDF) 471 Page - Renesas Technology Corp |
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M30620FCAFP Datasheet(HTML) 471 Page - Renesas Technology Corp |
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471 / 615 page ![]() Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer 2-154 2.11.1 Overview of the watchdog timer usage The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an overview of the watchdog timer usage. (1) Watchdog timer start procedure When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start performing a down count. The watchdog timer, once started operating, cannot be stopped by any means other than stopping conditions. (2) Watchdog timer stop conditions The watchdog timer stops in any one of the following states: (a) Period in which the CPU is in stopped state (b) Period in which the CPU is in waiting state (c) Period in which the microcomputer is in hold state (3) Watchdog timer initialization The watchdog timer is initialized to 7FFF16 in the cases given below, and begins a down count. (a) When the watchdog timer writes to the watchdog timer start register while a count is in progress (b) When the watchdog timer underflows (4) Runaway detection When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer interrupt, set the software reset bit to “1” to reset software. (5) Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected. 2.11 Watchdog Timer Usage CM07 CM06 CM17 CM16 BCLK WDC7 Period 0 0 0 0 0 1 00 016MHz 00 1 8MHz 01 0 4MHz 01 1 1MHz 1 Invalid Invalid 2MHz Invalid Invalid Invalid 32kHz 0 1 0 1 0 1 0 1 0 1 Invalid Approx. 32.8ms (Note) Approx. 262.1ms (Note) Approx. 65.5ms (Note) Approx. 524.3ms (Note) Approx. 131.1ms (Note) Approx. 1.049s (Note) Approx. 524.3ms (Note) Approx. 4.194s (Note) Approx. 262.1ms (Note) Approx. 2.097s (Note) Approx. 2s (Note) Note: An error due to the prescaler occurs. Table 2.11.1. The watchdog timer cycle |
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