M30620FCAFP datasheet(390/615 Pages) RENESAS

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Clock-Synchronous Serial I/O

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-73

Transmission

Reception

(1) With an external clock selected, perform the following set-up procedure with the CLKi pin

input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the

CLK polarity select bit = “1”:

1. Set the transmit enable bit (to “1”)

2. Write transmission data to the UARTi transmit buffer register

________

_______

3. “L” level input to the CTSi pin (when the CTS function is selected)

(1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock.

Fix settings for transmission even when using the device only for reception. Dummy data is

output to the outside from the TxDi pin (transmission pin) when receiving data.

(2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled

status) and setting dummy data in the UARTi transmission buffer register generates a shift

clock.

With the external clock selected, a shift clock is generated when the transmit enable bit is set

to “1”, dummy data is set in the UARTi transmit buffer register, and the external clock is input

to the CLKi pin.

(3) In receiving data in succession, an overrun error occurs when the next reception data is made

ready in the UARTi receive register with the receive complete flag set to “1” (before the

content of the UARTi receive buffer register is read), and overrun error flag is set to “1”. In this

instance, the next data is written to the UARTi receive buffer register, so handle with this

problem by writing programs on transmission side and reception side so that the previous

data is transmitted again.

If an overrun error occurs, the UARTi receive interrupt request bit does not change.

(4) To receive data in succession, set dummy data in the lower-order byte of the UARTi transmit

buffer register every time reception is made.

(5) With an external clock selected, perform the following set-up procedure with the CLKi pin

input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the

CLK polarity select bit = “1”:

1. Set receive enable bit (to “1”)

2. Set transmit enable bit (to “1”)

3. Write dummy data to the UARTi transmit buffer register

_______

(6) Output from the RTS pin goes to “L” level as soon as the receive enable bit is set to “1”. This

is not related to the content of the transmit buffer empty flag or the content of the transmit

enable bit.

_______

Output from the RTS pin goes to “H” level when reception starts, and goes to “L” level when

reception is completed. This is not related to the content of the transmit buffer empty flag or

the content of the receive complete flag.

M30620FCAFP Datasheet(PDF) 390 Page - Renesas Technology Corp

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