H8SX1663 datasheet(705/1158 Pages) RENESAS

705 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 653 of 1102

REJ09B0294-0100

Section 15 Serial Communication Interface

(SCI, IrDA, CRC)

This LSI has six independent serial communication interface (SCI) channels. The SCI can handle

both asynchronous and clocked synchronous serial communication. Asynchronous serial data

communication can be carried out with standard asynchronous communication chips such as a

Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication

Interface Adapter (ACIA). A function is also provided for serial communication between

processors (multiprocessor communication function). The SCI also supports the smart card (smart

card) interface supporting ISO/IEC 7816-3 (Identification Card) as an extended asynchronous

communication mode. SCI_5 enables transmitting and receiving IrDA communication waveform

based on the IrDA Specifications version 1.0. This LSI incorporates the on-chip CRC (Cyclic

Redundancy Check) computing unit that realizes high reliability of high-speed data transfer. Since

the CRC computing unit is not connected to SCI, operation is executed by writing data to

registers.

Figure 15.1 shows a block diagram of the SCI_0 to SCI_4. Figure 15.2 shows a block diagram of

the SCI_5 and SCI_6.

15.1

Features

• Choice of asynchronous or clocked synchronous serial communication mode

• Full-duplex communication capability

The transmitter and receiver are mutually independent, enabling transmission and reception to

be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,

enabling continuous transmission and continuous reception of serial data.

• On-chip baud rate generator allows any bit rate to be selected

The external clock can be selected as a transfer clock source (except for the smart card

interface).

• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)

• Four interrupt sources

The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive

error. The transmit-data-empty and receive-data-full interrupt sources can activate the DTC or

DMAC.

• Module stop state specifiable

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