H8SX1663 datasheet(680/1158 Pages) RENESAS

680 / 1158 page

Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 628 of 1102

REJ09B0294-0100

12.5.6

Timing of Overflow Flag (OVF) Setting

The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure

12.14 shows the timing of this operation.

OVF

Overflow signal

TCNT

H'FF

H'00

Figure 12.14 Timing of OVF Setting

12.6

Operation with Cascaded Connection

If the bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two

channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter

mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1

(compare match count mode).

12.6.1

16-Bit Counter Mode

When the bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit

timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.

(1)

Setting of Compare Match Flags

• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.

• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.

(2)

Counter Clear Specification

• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the

16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event

occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by

the TMRI0 pin has been set.

• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be

cleared independently.

H8SX1663 Datasheet(PDF) 680 Page - Renesas Technology Corp