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M37151M6 Datasheet(PDF) 53 Page - Renesas Technology Corp |
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M37151M6 Datasheet(HTML) 53 Page - Renesas Technology Corp |
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53 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 53 of 136 REJ03B0129-0100Z 8.10.5 Timing Signal Generating Circuit This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 1 (address 00E016) to “1.” The reference clock can be used as a display clock for the OSD function in addition to the data slicer. The HSYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00E016). For pins HLF, connect a resistor and a capacitor as shown in Figure 8.10.1. Make the length of wiring which is connected to these pins as short as possible to prevent a leakage current from being generated. Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep sig- nals become unstable. For this reason, take stabilization time into con- sideration when programming. Fig. 8.10.7 Determination of V-pulse Waveform Composite sync signal AB 0 1 1 Bit 5 of DSC2 |
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